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Alliance Memory DDR3/DDR3L Synchronous DRAM

Alliance Memory DDR3/DDR3L Synchronous DRAM (SDRAM) achieves high-speed double-data-rate transfer rates of up to 1600Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3/DDR3L DRAM key features, and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source synchronous fashion. These Alliance Memory devices operate with a single 1.35V (-0.067V/+0.1V) (DDR3L) or 1.5V (±0.075V) (DDR3) power supply and are available in BGA packages.

Features

  • JEDEC standard compliant
  • Power supplies
    • DDR3: VDD and VDDQ = +1.5V ±0.075V
    • DDR3L: VDD and VDDQ = +1.35V (1.283V to 1.45V)
  • Commercial operating temperature (0°C to +95°C)
  • Industrial operating temperature (-40°C to +95°C)
  • Supports JEDEC clock jitter specification
  • Fully synchronous operation
  • Fast clock rate 800MHz
  • Differential clock inputs, CK and CK#
  • Bidirectional differential data strobe - DQS and DQS#
  • Eight internal banks for concurrent operation
  • 8n-bit prefetch architecture
  • Internal pipeline architecture
  • Precharge and active power down
  • Programmable mode and extended mode registers
  • Additive latency (AL): 0, CL-1, CL-2
  • Programmable burst lengths: 4 and 8
  • Burst type: sequential/interleave
  • Output driver impedance control
  • 8192 refresh cycles/64ms (7.8µs at -40°C ≦ TC ≦ +85°C)
  • Write leveling
  • OCD calibration
  • Dynamic ODT (Rtt_Nom and Rtt_WR)
  • Auto-refresh and self-refresh
  • TFBGA package (78-ball and 96-ball )
  • RoHS compliant (lead-free and halogen-free)
Published: 2014-02-25 | Updated: 2026-07-21