SN65LVDS302 Display Serial Interface Receiver

Texas Instruments SN65LVDS302 Programmable 27-Bit Display Serial Interface Receiver de-serializes FlatLink™ 3G compliant serial input data to 27 parallel data outputs. The Texas Instruments SN65LVDS302 receiver contains one shift register to load 30 bits from 1, 2, or 3 serial inputs. After checking the parity bit, it latches the 24-pixel and three control bits to the parallel CMOS outputs. If the parity check confirms correct parity, the Channel Parity Error (CPE) output remains low. If a parity error is detected, the CPE output generates a high pulse while the data output bus disregards the newly received pixel. Instead, the last data word is held on the output bus for another clock cycle.