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CD74ACT164E

Name: Texas Instruments CD74ACT164E
Brand: Texas Instruments
SKU: 595-CD74ACT164E
Price: 1.51 EUR
Availability: InStock

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Mouser No:

595-CD74ACT164E

Mfr. No:

CD74ACT164E

Mfr.:

Texas Instruments

Description:

Counter Shift Registers 8-Bit Srl-In Prl-Out

Datasheet:

CD74ACT164E Datasheet

ECAD Model:

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More Information

Learn more about Texas Instruments CD74ACT164E

In Stock: 664

Stock:: 664 Can Dispatch Immediately

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Factory Lead Time:: 12 Weeks Estimated factory production time for quantities greater than shown.

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Pricing (EUR)

Qty.	Unit Price	Ext. Price
	1,51 €	1,51 €
	1,11 €	11,10 €
	1,01 €	25,25 €
	0,894 €	89,40 €
	0,844 €	211,00 €
	0,839 €	419,50 €
	0,786 €	786,00 €
	0,759 €	1.897,50 €
	0,742 €	3.710,00 €

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Texas Instruments
Product Category:	Counter Shift Registers
RoHS:
Counting Sequence:	Serial to Parallel
Number of Circuits:	1 Circuit
Number of Bits:	8 bit
Package/Case:	PDIP-14
Logic Family:	74ACT
Logic Type:	CMOS
Number of Input Lines:	2
Propagation Delay Time:	14.9 ns
Supply Voltage - Min:	500 mV
Supply Voltage - Max:	6 V
Minimum Operating Temperature:	- 55 C
Maximum Operating Temperature:	+ 125 C
Packaging:	Tube
Brand:	Texas Instruments
Function:	8 Bit Serial In Parallel Out
Mounting Style:	SMD/SMT
Number of Output Lines:	8
Operating Supply Voltage:	500 mV to 6 V
Product Type:	Counter Shift Registers
Series:	CD74ACT164
Factory Pack Quantity:	25
Subcategory:	Logic ICs
Unit Weight:	1 g

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Compliance Codes

TARIC:: 8542319000
CNHTS:: 8542399000
CAHTS:: 8542390000
USHTS:: 8542390090
JPHTS:: 8542390990
MXHTS:: 8542310399
ECCN:: EAR99

Origin Classifications

Country of Origin:: Malaysia
Assembly Country of Origin:: Not available
Country of Diffusion:: Not available

The country is subject to change at the time of shipment.

CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers

Texas Instruments CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers have two serial inputs (A and B) connected through an AND gate and an asynchronous clear (CLR). The device requires a high signal on both A and B to set the input data line high; a low signal on either will set the input data line low. Data at A and B can be changed while CLK is high or low, provided the minimum set-up time requirements are met.